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1 LT1468 90mhz, 22v/ m s 16-bit accurate operational amplifier frequency (hz) 100 110 total harmonic distortion (db) 100 ?0 1k 10k 100k 1468 ta02 120 130 ?0 v s = 15v a v = 2 r l = 2k v out = 10v p-p total harmonic distortion vs frequency features descriptio u the lt ? 1468 is a precision high speed operational ampli- fier with 16-bit accuracy and 900ns settling to 150 m v for 10v signals. this unique blend of precision and ac perfor- mance makes the LT1468 the optimum choice for high accuracy applications such as dac current-to-voltage conversion and adc buffers. the initial accuracy and drift characteristics of the input offset voltage and inverting input bias current are tailored for inverting applications. the 90mhz gain bandwidth ensures high open-loop gain at frequency for reducing distortion. in noninverting appli- cations such as an adc buffer, the low distortion and dc accuracy allow full 16-bit ac and dc performance. the 22v/ m s slew rate of the LT1468 improves large-signal performance in applications such as active filters and instrumentation amplifiers compared to other precision op amps. the LT1468 is manufactured on linear technologys complementary bipolar process. n 90mhz gain bandwidth, f = 100khz n 22v/ m s slew rate n settling time: 900ns (a v = C1, 150 m v, 10v step) n low distortion, C 96.5db for 100khz, 10v p-p n maximum input offset voltage: 75 m v n maximum input offset voltage drift: 2 m v/ c n maximum (C) input bias current: 10na n minimum dc gain: 1000v/mv n minimum output swing into 2k: 12.8v n unity gain stable n input noise voltage: 5nv/ ? hz n input noise current: 0.6pa/ ? hz n total input noise optimized for 1k < r s < 20k n specified at 5v and 15v , ltc and lt are registered trademarks of linear technology corporation. n 16-bit dac current-to-voltage converter n precision instrumentation n adc buffer n low distortion active filters n high accuracy data acquisition systems n photodiode amplifiers applicatio n s u typical applicatio u 20pf 6k ltc 1597 LT1468 16 dac inputs + offset: v os + i b (6k ) < 1lsb settling time to 150 v = 1.7 s settling limited by 6k and 20pf to compensate dac output capacitance v out 2k 50pf optional noise filter 1468 ta01 16-bit dac i-to-v converter
2 LT1468 (note 1) total supply voltage (v + to v C ) ............................... 36v maximum input current (note 2) ......................... 10ma output short-circuit duration (note 3) ............ indefinite operating temperature range ................ C 40 c to 85 c specified temperature range (note 4) ... C 40 c to 85 c junction temperature ........................................... 150 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i for atio uu w absolute axi u rati gs w ww u order part number LT1468cn8 LT1468cs8 LT1468in8 LT1468is8 s8 part marking 1468 1468i consult factory for military grade parts. t jmax = 150 c, q ja = 130 c/w (n8) t jmax = 150 c, q ja = 190 c/w (s8) 1 2 3 4 8 7 6 5 top view *do not connect s8 package 8-lead plastic so n8 package 8-lead pdip null ?n +in v dnc* v + v out null electrical characteristics symbol parameter conditions v supply min typ max units v os input offset voltage 15v 30 75 m v 5v 50 175 m v i os input offset current 5v to 15v 13 50 na i b C inverting input bias current 5v to 15v 3 10 na i b + noninverting input bias current 5v to 15v C 10 40 na input noise voltage 0.1hz to 10hz 5v to 15v 0.3 m v p-p e n input noise voltage f = 10khz 5v to 15v 5 nv/ ? hz i n input noise current f = 10khz 5v to 15v 0.6 pa/ ? hz r in input resistance v cm = 12.5v 15v 100 240 m w differential 15v 50 150 k w c in input capacitance 15v 4 pf input voltage range + 15v 12.5 13.5 v 5v 2.5 3.5 v input voltage range C 15v C14.3 C12.5 v 5v C 4.3 C2.5 v cmrr common mode rejection ratio v cm = 12.5v 15v 96 110 db v cm = 2.5v 5v 96 112 db psrr power supply rejection ratio v s = 4.5v to 15v 100 112 db a vol large-signal voltage gain v out = 12.5v, r l = 10k 15v 1000 9000 v/mv v out = 12.5v, r l = 2k 15v 500 5000 v/mv v out = 2.5v, r l = 10k 5v 1000 6000 v/mv v out = 2.5v, r l = 2k 5v 500 3000 v/mv v out output swing r l = 10k 15v 13.0 13.6 v r l = 2k 15v 12.8 13.5 v r l = 10k 5v 3.0 3.6 v r l = 2k 5v 2.8 3.5 v i out output current v out = 12.5v 15v 15 22 ma v out = 2.5v 5v 15 22 ma i sc short-circuit current v out = 0v, v in = 0.2v 15v 25 40 ma t a = 25 c, v cm = 0v unless otherwise noted.
3 LT1468 symbol parameter conditions v supply min typ max units sr slew rate a v = C1, r l = 2k (note 5) 15v 15 22 v/ m s 5v 11 17 v/ m s full-power bandwidth 10v peak, (note 6) 15v 350 khz 3v peak, (note 6) 5v 900 khz gbw gain bandwidth f = 100khz, r l = 2k 15v 60 90 mhz 5v 55 88 mhz thd total harmonic distortion a v = 2, v o = 10v p-p , f = 1khz 15v 0.00007 % a v = 2, v o = 10v p-p , f = 100khz 15v 0.0015 % t r , t f rise time, fall time a v = 1, 10% to 90%, 0.1v 15v 11 ns 5v 12 ns overshoot a v = 1, 0.1v 15v 30 % 5v 35 % propagation delay a v = 1, 50% v in to 50% v out , 0.1v 15v 9 ns 5v 10 ns t s settling time 10v step, 0.01%, a v = C1 15v 760 ns 10v step, 150 m v, a v = C1 15v 900 ns 5v step, 0.01%, a v = C1 5v 770 ns r o output resistance a v = 1, f = 100khz 15v 0.02 w i s supply current 15v 3.9 5.2 ma 5v 3.6 5.0 ma electrical characteristics t a = 25 c, v cm = 0v unless otherwise noted. symbol parameter conditions v supply min typ max units v os input offset voltage 15v l 150 m v 5v l 250 m v input v os drift (note 7) 5v to 15v l 0.7 2.0 m v/ c i os input offset current 5v to 15v l 65 na input offset current drift 5v to 15v 60 pa/ c i b C inverting input bias current 5v to 15v l 15 na negative input current drift 5v to 15v 40 pa/ c i b + noninverting input bias current 5v to 15v l 50 na cmrr common mode rejection ratio v cm = 12.5v 15v l 94 db v cm = 2.5v 5v l 94 db psrr power supply rejection ratio v s = 4.5v to 15v l 98 db a vol large-signal voltage gain v out = 12.5v, r l = 10k 15v l 500 v/mv v out = 12.5v, r l = 2k 15v l 250 v/mv v out = 2.5v, r l = 10k 5v l 500 v/mv v out = 2.5v, r l = 2k 5v l 250 v/mv v out output swing r l = 10k 15v l 12.9 v r l = 2k 15v l 12.7 v r l = 10k 5v l 2.9 v r l = 2k 5v l 2.7 v i out output current v out = 12.5v 15v l 12.5 ma v out = 2.5v 5v l 12.5 ma i sc short-circuit current v out = 0v, v in = 0.2v 15v l 17 ma sr slew rate a v = C1, r l = 2k (note 5) 15v l 13 v/ m s 5v l 9v/ m s 0 c t a 70 c, v cm = 0v unless otherwise noted.
4 LT1468 electrical characteristics 0 c t a 70 c, v cm = 0v unless otherwise noted. symbol parameter conditions v supply min typ max units v os input offset voltage 15v l 230 m v 5v l 330 m v input v os drift (note 7) 5v to 15v l 0.7 2.5 m v/ c i os input offset current 5v to 15v l 80 na input offset current drift 5v to 15v 120 pa/ c i b C inverting input bias current 5v to 15v l 30 na negative input current drift 5v to 15v 80 pa/ c i b + noninverting input bias current 5v to 15v l 60 na cmrr common mode rejection ratio v cm = 12.5v 15v l 92 db v cm = 2.5v 5v l 92 db psrr power supply rejection ratio v s = 4.5v to 15v l 96 db a vol large-signal voltage gain v out = 12v, r l = 10k 15v l 300 v/mv v out = 10v, r l = 2k 15v l 150 v/mv v out = 2.5v, r l = 10k 5v l 300 v/mv v out = 2.5v, r l = 2k 5v l 150 v/mv v out output swing r l = 10k 15v l 12.8 v r l = 2k 15v l 12.6 v r l = 10k 5v l 2.8 v r l = 2k 5v l 2.6 v i out output current v out = 12.5v 15v l 7ma v out = 2.5v 5v l 7ma i sc short-circuit current v out = 0v, v in = 0.2v 15v l 12 ma sr slew rate a v = C1, r l = 2k (note 5) 15v l 9v/ m s 5v l 6v/ m s gbw gain bandwidth f = 100khz, r l = 2k 15v l 45 mhz 5v l 40 mhz i s supply current 15v l 7.0 ma 5v l 6.8 ma C40 c t a 85 c, v cm = 0v unless otherwise noted (note 4). symbol parameter conditions v supply min typ max units gbw gain bandwidth f = 100khz, r l = 2k 15v l 55 mhz 5v l 50 mhz i s supply current 15v l 6.5 ma 5v l 6.3 ma the l denotes specifications that apply over the full operating temperature range. note 1 : absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2 : the inputs are protected by back-to-back diodes and two 100 w series resistors. if the differential input voltage exceeds 0.7v, the input current should be limited to 10ma. input voltages outside the supplies will be clamped by esd protection devices and input currents should also be limited to 10ma. note 3 : a heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. note 4 : the LT1468c is guaranteed to meet specified performance from 0 c to 70 c and is designed, characterized and expected to meet these extended temperature limits, but is not tested at C 40 c and at 85 c. the LT1468i is guaranteed to meet the extended temperature limits. note 5 : slew rate is measured between 8v on the output with 12v input for 15v supplies and 2v on the output with 3v input for 5v supplies. note 6 : full power bandwidth is calculated from the slew rate measurement: fpbw = sr/2 p v p note 7 : this parameter is not 100% tested.
5 LT1468 typical perfor a ce characteristics uw input common mode voltage (v) ?5 input bias current (na) ?0 0 20 0 10 1468 g03 ?0 ?0 ?0 ?0 5 5 40 i b i b + 60 80 15 v s = 15v t a = 25 c input bias current vs input common mode voltage temperature ( c) ?0 0 10 i b i b + 30 25 75 1468 g04 ?0 ?0 ?5 0 50 100 125 ?0 ?0 20 input bias current (na) v s = 15v input bias current vs temperature supply voltage ( v) 0 1 supply current (ma) 2 3 4 5 6 125 c 25 c ?5 c 7 5101520 1468 g01 supply current vs supply voltage and temperature supply voltage ( v) 0 v common mode range (v) 1.0 2.0 2.0 3 6 912 1468 g02 15 1.0 0.5 1.5 1.5 v + 0.5 18 t a = 25 c d v os < 100 m v input common mode range vs supply voltage 0.1hz to 10hz voltage noise time (1s/div) voltage noise (100nv/div) 1468 g06 v s = 15v input noise spectral density frequency (hz) 1 1 input voltage noise (nv/ ? hz) input current noise (pa/ ? hz) 100 1000 10 100 1k 10k 100k 1468 g05 10 0.01 1 i n e n 10 0.1 v s = 15v t a = 25 c a v = 101 r s = 100k for i n warm-up drift vs time time after power up (s) 0 20 40 60 80 100 120 140 ?0 offset voltage drift ( m v) ?5 ?5 ?0 ?5 5 1468 g07 ?0 ?0 ? 0 s0-8 15v n8 5v s0-8 5v n8 15v load resistance ( w ) 10 110 open-loop gain (db) 130 135 140 100 1k 10k 1468 g08 125 120 115 t a = 25 c v s = 15v v s = 5v open-loop gain vs resistive load open-loop gain vs temperature temperature ( c) ?0 130 140 160 25 75 1468 g09 120 110 ?5 0 50 100 125 100 90 150 open-loop gain (db) r l = 2k v s = 15v v s = 5v
6 LT1468 typical perfor a ce characteristics uw output short-circuit current vs temperature settling time to 0.01% vs output step, v s = 15v output voltage swing vs supply voltage output voltage swing vs load current supply voltage ( v) 0 1 v output voltage swing (v) 4 3 2 ? ? ? v + ? 5 1468 g10 10 15 20 r l = 2k r l = 10k r l = 2k t a = 25 c r l = 10k output current (ma) ?0 v ? 0.5 output voltage swing (v) 1.0 2.0 2.5 v + 0.5 2.0 ?0 0 5 1468 g11 1.5 ?.5 1.0 2.5 ?5 5 10 15 20 v s = 15v 85 c 85 c 40 c 25 c 25 c ?0 c temperature ( c) ?0 10 output short-circuit current (ma) 15 25 30 35 60 45 0 50 75 1468 g12 20 50 55 40 ?5 25 100 125 v s = 15v v in = 0.2v source sink settling time (ns) 0 output step (v) 2 6 10 800 1468 g13 ? ? 0 4 8 ? ? ?0 200 400 600 1000 a v = 1 a v = 1 a v = 1 a v = 1 v s = 15v r l = 1k settling time to 0.01% vs output step, v s = 5v settling time (ns) 300 output step (v) 1 3 5 700 1468 g14 ? ? 0 2 4 ? ? ? 400 500 600 800 a v = 1 a v = 1 a v = 1 a v = 1 v s = 5v r l = 1k settling time to 150 m v vs output step settling time (ns) 0 output step (v) 2 6 10 800 1468 g15 ? ? 0 4 8 ? ? ?0 200 400 600 1000 v s = 15v a v = 1 r f = r g = 2k c f = 8pf output impedance vs frequency frequency (hz) 0.01 output impedance ( w ) 0.1 1 10 100 10k 1m 10m 100m 1468 g19 0.001 100k v s = 15v t a = 25 c a v = 100 a v = 10 a v = 1 supply voltage ( v) 0 gain bandwidth (mhz) phase margin (deg) 90 92 94 20 1468 g17 88 86 82 5 10 15 84 98 96 36 38 40 34 32 28 30 44 42 t a = 25 c a v = 1 r f = r g = 5.1k c f = 5pf r l = 2k phase margin gain bandwidth gain bandwidth and phase margin vs supply voltage temperature ( c) ?5 84 gain bandwidth (mhz) phase margin (deg) 86 90 92 94 104 98 0 50 75 1468 g18 88 100 102 96 26 28 32 34 36 46 40 30 42 44 38 ?5 25 100 125 v s = 5v v s = 5v v s = 15v v s = 15v gain bandwidth phase margin gain bandwidth and phase margin vs temperature
7 LT1468 typical perfor a ce characteristics uw gain and phase vs frequency frequency (hz) 20 gain (db) phase (deg) 40 50 70 10k 1m 10m 100m 1468 g16 0 100k 60 30 10 ?0 0 40 60 100 ?0 80 20 ?0 ?0 phase gain 15v 15v 5v 5v t a = 25 c a v = 1 r f = r g = 5.1k c f = 5pf r l = 2k common mode rejection ratio vs frequency frequency (hz) 100 0 common mode rejection ratio (db) 20 40 60 80 120 1k 10k 100k 1m 1468 g21 10m 100m 100 v s = 15v t a = 25 c power supply rejection ratio vs frequency frequency (hz) 100 power supply rejection ratio (db) 60 80 100 100k 10m 1468 g20 40 20 0 1k 10k 1m 120 140 160 100m psrr +psrr v s = 15v t a = 25 c frequency response vs supply voltage, a v = 1 frequency response vs capacitive load, a v = 1 frequency (hz) 100k 2 gain (db) 4 6 8 10 1m 10m 100m 1468 g24 0 ? ? ? 12 14 v s = 15v t a = 25 c a v = 1 no r l 100pf 10pf 50pf 20pf frequency response vs capacitive load, a v = C1 frequency (hz) 100k 2 gain (db) 4 6 8 10 1m 10m 100m 1468 g25 0 ? ? ? 12 14 v s = 15v t a = 25 c a v = 1 r f = r g = 5.1k c f = 5pf no r l 300pf 200pf 50pf 100pf frequency (hz) 100k ? gain (db) 0 1 2 3 1m 10m 100m 1468 g22 ? ? ? ? 4 5 t a = 25 c a v = 1 r l = 2k 5v 15v frequency response vs supply voltage, a v = C 1 frequency (hz) 100k ? gain (db) 0 1 2 3 1m 10m 100m 1468 g23 ? ? ? ? 4 5 t a = 25 c a v = 1 r l = 2k c f = 5pf r f = r g = 2k 5v 15v r f = r g = 5.1k 5v 15v slew rate vs supply voltage supply voltage ( v) 0 slew rate (v/ m s) 22 24 26 20 1468 g26 20 18 14 5 10 15 16 30 28 ?r +sr t a = 25 c a v = 1 r l = 2k slew rate vs temperature temperature ( c) ?0 slew rate (v/ m s) 40 25 1468 g27 25 ?r +sr 15 ?5 0 50 10 5 45 35 30 20 75 100 125 v s = 15v a v = 1 r l = 2k
8 LT1468 typical perfor a ce characteristics uw undistorted output swing vs frequency, 15v frequency (khz) 1 0 output voltage swing (v p-p ) 20 25 30 10 100 1000 1468 g30 15 10 5 a v = 1 a v = 1 v s = 15v r l = 2k frequency (hz) 20 0.0001 thd + noise (%) 0.001 0.010 100 1k 20k 10k 1468 g28 v s = 15v t a = 25 c r l = 600 w v o = 20v p-p noise bw = 80khz a v = 10 a v = 1 measurement limit total harmonic distortion + noise vs frequency total harmonic distortion + noise vs amplitude output signal (v rms ) 0.01 110 thd + noise (db) ?0 ?0 ?0 0.1 1 10 1468 g29 ?0 ?0 100 15v 5v t a = 25 c a v = 10 r l = 600 w f = 10khz noise bw = 80khz undistorted output swing vs frequency, 5v frequency (khz) 1 4 output voltage swing (v p-p ) 5 6 7 8 10 100 1000 1468 g33 3 2 1 0 9 10 v s = 5v r l = 2k a v = 1 a v = 1 source resistance, r s ( w ) 1 total noise voltage (nv/ ? hz) 10 10 1k 10k 100k 1468 g36 0.1 100 100 v s = 15v t a = 25 c f = 10khz total noise resistor noise only r s + total noise vs unmatched source resistance small-signal transient, a v = 1 v s = 15v 1468 g31 small-signal transient, a v = C 1 v s = 15v 1468 g32 large-signal transient, a v = 1 v s = 15v 1468 g34 large-signal transient, a v = C 1 v s = 15v 1468 g32
9 LT1468 applicatio n s i n for m atio n wu u u the LT1468 may be inserted directly into many opera- tional amplifier applications improving both dc and ac performance, provided that the nulling circuitry is re- moved. the suggested nulling circuit for the LT1468 is shown below. the parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole that can cause peaking or even oscillations. for feedback resistors greater than 2k, a feedback capacitor of the value: c f > (r g )(c in /r f ) should be used to cancel the input pole and optimize dy- namic performance. for applications where the dc noise gain is one, and a large feedback resistor is used, c f should be greater than or equal to c in . an example would be a dac i-to-v converter as shown on the front page of this data sheet where the dac can have many tens of pf of output capacitance. another example would be a gain of C1 with 5k resistors; a 5pf to 10pf capacitor should be added across the feedback resistor. the frequency response in a gain of C1 is shown in the typical performance curves with 2k and 5.1k resistors with a 5pf feedback capacitor. layout and passive components the LT1468 requires attention to detail in board layout in order to maximize dc and ac performance. for best ac results (for example fast settling time) use a ground plane, short lead lengths, and rf-quality bypass capacitors (0.01 m f to 0.1 m f) in parallel with low esr bypass capaci- tors (1 m f to 10 m f tantalum). for best dc performance, use star grounding techniques, equalize input trace lengths and minimize leakage (i.e., 1.5g w of leakage between an input and a 15v supply will generate 10naequal to the maximum i b C specification.) board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs. for inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below.) microvolt level error voltages can also be generated in the external circuitry. thermocouple effects caused by tem- perature gradients across dissimilar metals at the con- tacts to the inputs can exceed the inherent drift of the amplifier. air currents over device leads should be mini- mized, package leads should be short, and the two input leads should be as close together as possible and main- tained at the same temperature. make no connection to pin 8. this pin is used for factory trim of the inverting input current. + LT1468 1 5 100k v v + 4 2.2 m f 0.1 m f 2.2 m f 0.1 m f 7 6 3 2 1468 ai01 offset nulling + LT1468 1468 ai02 r g r f c in c f v in v out nulling input capacitance input considerations each input of the LT1468 is protected with a 100 w series resistor and back-to-back diodes across the bases of the input devices. if the inputs can be pulled apart, the input current should be limited to less than 10ma with an external series resistor. each input also has two esd clamp diodesone to each supply. if an input is driven above the supply, limit the current with an external resistor to less than 10ma. the LT1468 employs bias current cancellation at the inputs. the inverting input current is trimmed at zero common mode voltage to minimize errors in inverting applications such as i-to-v converters. the noninverting input current is not trimmed and has a wider variation and therefore a larger maximum value. as the input offset
10 LT1468 applicatio n s i n for m atio n wu u u current can be greater than either input current, the use of balanced source resistance is not recommended as it actually degrades dc accuracy and also increases noise. the input bias currents vary with common mode voltage as shown in the typical performance characteristics. the cancellation circuitry was not designed to track this com- mon mode voltage because the settling time would have been adversely affected. the LT1468 inputs can be driven to the negative supply and to within 0.5v of the positive supply without phase reversal. as the input moves closer than 0.5v to the positive supply, the output reverses phase. driving capacitive loads + LT1468 1468 ai04 r g r o r f c f c l v in v out r o 3 (1 + r f /r g )/(2 p c l 5mhz) r f 3 10r o c f = (2r o /r f )c l excellent linear technology reference sources for settling measurements, application notes 47 and 74. appendix b of an47 is a vital primer on 12-bit settling measurements, and an74 extends the state of the art while concentrating on settling time with a 16-bit current output dac input. the 150 m v settling curve in the typical performance characteristics is measured using the differential ampli- fier method of an74 followed by a clamped, nonsaturating gain of 100. the total gain of 500 allows a resolution of 100 m v/div with an oscilloscope setting of 0.05v/div the settling of the dac i-to-v converter on the front page was measured using the exact methods of an74. the optimum nulling of the dac output capacitance requires 20pf across the 6k feedback resistor. the theoretical limit for 16-bit settling is 11.1 times this rc time constant or 1.33 m s. the actual settling time is 1.7 m s at the output of the LT1468. the LT1468 is the fastest linear technology amplifier in this application. the optional noise filter adds a slight delay of 100ns, but reduces the noise bandwidth to 1.6mhz which increases the output resolution for 16-bit accuracy. distortion the LT1468 has outstanding distortion performance as shown in the typical performance curves of total harmonic distortion + noise vs frequency and amplitude. the high open-loop gain and inherently balanced architecture reduce errors to yield 16-bit accuracy to frequencies as high as 100khz. an example of this performance is the typical application titled 100khz low distortion bandpass filter. this circuit is useful for cleaning up the output of a high performance signal generator such as the b & k type 1051 or hp3326a. input stage protection r1 100 w r2 100 w +in in 1468 ai03 q1 q2 total input noise the curve of total noise vs unmatched source resistance in the typical performance characteristics shows that with source resistance below 1k, the voltage noise of the am- plifier dominates. in the 1k to 20k region the increase in noise is due to the source resistance. above 20k the input current noise component is larger than the resistor noise. capacitive loading the LT1468 drives capacitive loads of up to 100pf in unity gain and 300pf in a gain of C1. when there is a need to drive a larger capacitive load, a small series resistor should be inserted between the output and the load. in addition, a capacitor should be added between the output and the inverting input as shown in driving capacitive loads. settling time the LT1468 is a single stage amplifier with an optimal thermal layout that leads to outstanding settling performance. measuring settling, even at the 12-bit level is very challenging, and at the 16-bit level requires a great deal of subtlety and expertise. fortunately, there are two
11 LT1468 applicatio n s i n for m atio n wu u u another key application for LT1468 is buffering the input to a 16-bit a/d converter. in a gain of 1 or 2 this straight- forward circuit provides uncorrupted ac and dc levels to the converter, while buffering the a/d input sample-and- hold circuit from high source impedance which can reduce the maximum sampling rate. the front page graph shows better than 16-bit distortion for a gain of 2 with a 10v p-p output. information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. n8 1197 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) sche m atic w w si plified q10 i5 i2 i1 i4 i6 1468 ss i3 out q11 q8 q9 q7 q6 q1 in +in v + v q5 q2 q4 c bias q3 package descriptio n u dimensions in inches (millimeters) unless otherwise noted.
12 LT1468 typical applicatio n s u ? linear technology corporation 1998 sn1468 1468fs lt/tp 1098 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com instrumentation amplifier + LT1468 + LT1468 1468 ta03 r1 50k r2 5k r3 5k r5 1.1k r4 50k c1 10pf c2 2pf v out v in gain = [r4/r3][1 + (1/2)(r2/r1 + r3/r4) + (r2 + r3)/r5] = 102 trim r5 for gain trim r1 for common mode rejection bw = 480khz + + LT1468 1468 ta04 2k 200 w 33.2k 2k 10pf 1000pf v in 2.2 m f ltc1605 cap 16 bits 16-bit adc buffer 100khz low distortion bandpass filter related parts part number description comments lt1167 precision instrumentation amplifier single resistor gain set, 0.04% max gain error, 10ppm max gain nonlinearity ltc1595/ltc1596 16-bit serial multiplying i out dacs 1lsb max inl/dnl, low glitch, dac8043 16-bit upgrade ltc1597 16-bit parallel multiplying i out dac 1lsb max inl/dnl, low glitch, on-chip bipolar resistors ltc1604 16-bit, 333ksps sampling adc 2.5v input, sinad = 90db, thd = C100db ltc1605 single 5v, 16-bit, 100ksps sampling adc low power, 10v inputs, parallel/byte interface + LT1468 1468 ta05 11k 121 w r l 22.1k 1000pf 1000pf 100khz distortion v in v out f o = 100khz q = 7 a v = 1 signal level 1v rms 2v rms 3.5v rms 1v rms 2v rms 3.5v rms r l 1m 1m 1m 2k 2k 2k 2nd harmonic 106db 105db 106db 103db 99db 96.5db 3rd harmonic 103db 105db 104db 103db 103db 102db

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